`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:51:20 04/05/2013 
// Design Name: 
// Module Name:    Execution_Control 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Execution_Control(
    input go,
    input Sys_clk_100mhz,
    input tx_sucessful,
    input stop,
	 input rst,
    output reg pop_data = 1'b0
    );
	 
	 reg [0:0] state = 1'b0;
	 reg [1:0] pop_count = 1'b0;
	 
	 reg go_reg = 1'b0;
	 reg [31: 0] increment = 1'b0;
	 parameter duration = 1;
	 wire ped_pulse;
	 
	 always @(posedge Sys_clk_100mhz or negedge rst) begin
		if (~rst) begin
			pop_data <= 1'b0;
			pop_count <= 1'b0;
		end
		else begin
			if (go_reg) increment = increment + 1'b1;
			case (state)
				1'b0 : begin
					if(go && !stop) begin
						go_reg <= 1'b1;
						pop_count <= pop_count + 1'b1;
						state <= 1'b1;
					end
					else if ((increment >= duration) && ~stop) begin
						pop_data <= 1'b1;
						state <= 1'b1;
						pop_count <= pop_count + 1'b1;
						increment = 1'b0;
					end
					else if (stop) begin
						go_reg <= 1'b0;
						pop_count <= 1'b0;
						pop_data <= 1'b0;
						increment = 1'b0;
					end
				end
				1'b1 : begin
					if (pop_count >= 2) begin
						pop_count <= 1'b0;
						pop_data <= 1'b0;
						state <= 1'b0;
						increment = 1'b0;
					end
					else
						pop_count <= pop_count + 1'b1;
				end
			endcase
		end
	 end

endmodule